In a system requested to have high precision and high resolution, as described in the following non-patent document 1, an analog multiplexer is used for selecting one of a plurality of analog input signals and supplying it to an A/D converter for converting an analog signal to a digital signal. A plurality of analog input signals are supplied to one end of a plurality of analog switches in the analog multiplexers. The other end of each of the plural analog switches is coupled to an input terminal of a buffer amplifier. An output of the buffer amplifier is coupled to an input terminal of the A/D converter via a sample and hold circuit. The basic function of the sample and hold circuit in an analog input system is to capture an input signal and hold it constant in the following conversion cycle of the A/D converter.
The sample and hold circuit is configured by an input buffer amplifier, a sample and hold switch, a retention capacitor, and an output buffer. In a sample mode, an input signal is retained in the retention capacitor via the input buffer amplifier and the sample and hold switch in the on state. In a hold mode, the sample and hold switch is controlled in an off state, and the retained voltage in the retention capacitor is supplied to the input terminal of the A/D converter via the output buffer.
In the following patent document 1, a semiconductor integrated circuit in which an analog multiplexer and a successive-approximation-type A/D converter are formed on a semiconductor substrate is described. The analog multiplexer selects a plurality of analog input signals of a plurality of external terminals, and the selected analog input signal is supplied to a first input terminal of a comparator in the successive-approximation-type A/D converter. A plurality of bit signals of a successive-approximation register are controlled by an output of the comparator, and a local D/A converter is controlled by the plural bit signals of the successive-approximation register. In response to upper eight bit signals and lower two bit signals in the plural bit signals from the successive-approximation register, first and second comparison reference voltages are generated, respectively, from the local D/A converter. The first and second comparison reference voltages from the local D/A converter are supplied to second and third input terminals of the comparator via first and second operational amplifiers, respectively. Two input terminals of a selection switch are coupled to the first and second input terminals, an output terminal of the selection switch is coupled to one end of a first capacitor, one end of a second capacitor is coupled to the third input terminal, and the other end of the first capacitor and the other end of the second capacitor are coupled to an input terminal of a voltage comparator. In the local D/A converter, a first transfer switch for reducing the influence of the offset voltage of the first operational amplifier is coupled between the input and output terminals of the first operational amplifier. A second transfer switch for reducing the influence of the offset voltage of the second operational amplifier is coupled between the input and output terminals of the second operational amplifier.
On the other hand, the following non-patent document 2 describes a circuit technique for reducing the influence of incompleteness of an operational amplifier using correlated double sampling (CDS). FIG. 29 of the non-patent document 2 shows a switched-capacitor-type sample and hold circuit of a first format configured by a first switch, a second switch, a sampling capacitor, an operational amplifier, and a third switch. An input signal is supplied to one end of the sampling capacitor via the first switch controlled by a first clock signal and one end of the second switch controlled by a second clock signal. The other end of the sampling capacitor is coupled to an inverting input terminal of the operational amplifier and one end of the third switch controlled by the first clock signal. A non-inverting input terminal of the operational amplifier is coupled to the grounding potential, and an output terminal of the operational amplifier is coupled to the other end of the second switch and the other end of the third switch.
The switched-capacitor-type sample and hold circuit of the first format executes operations in a sample mode and a hold mode as described below. Specifically, in a period in which the first clock signal is at the high level, an input signal is supplied to the inverting input terminal of the operational amplifier via the sampling capacitor. Since the inverting input terminal and the output terminal of the operational amplifier are coupled to each other, the difference voltage between the input signal voltage and the offset voltage is sampled between both ends of the sampling capacitor. In the high-level period of the second clock signal, an input signal supply node is opened from the inverting input terminal of the operational amplifier, and the sampling capacitor is coupled between the inverting input terminal and the output terminal of the operational amplifier. Therefore, a hold output signal in which the influence of the offset voltage is reduced by the correlated double sampling is obtained.
The following non-patent document 3 describes a switched-capacitor-type comparator using correlated double sampling (CDS). The switched-capacitor-type comparator includes a selection first switch having two input terminals, a sampling capacitor, an operational amplifier, and a second switch. The switched-capacitor-type comparator executes operations in a sample mode and a hold and voltage comparison mode as follows. Specifically, in the sample mode, an input signal is supplied to an inverting input terminal of the operational amplifier via a first input terminal of the selection first switch and the sampling capacitor. Since the inverting input terminal and the output terminal of the operational amplifier are coupled to each other, the difference voltage between the input signal voltage and the offset voltage is sampled between both ends of the sampling capacitor. In the hold and voltage comparison mode, the ground voltage is supplied to the inverting input terminal of the operational amplifier via the second input terminal of the selection first switch and the sampling capacitor, and the inverting input terminal of the operational amplifier and the output terminal are opened. Therefore, the offset voltage of the operational amplifier is cancelled between the operations of the sampling mode and the hold and voltage comparison mode. According to the positive/negative sign of a negative input signal voltage −Vin corresponding to the difference between the offset voltage and the input signal voltage, a logic determination result is obtained from the output terminal of the operational amplifier.
On the other hand, the non-patent document 4 describes a switched-capacitor-type sample and hold circuit of the second format different from that of the first format described in the non-patent document 2. The switched-capacitor-type sample and hold circuit of the second format is configured by three current sources which can form an operational amplifier, a differential pair P-channel MOS transistor, two load N-channel MOS transistors, two grounded-source amplification N-channel MOS transistors, seven switches, and a load capacitor.
In the sample mode of the switched-capacitor-type sample and hold circuit of the second format, an input signal is supplied to the non-inverting input terminal of the operational amplifier, and an output terminal of the operational amplifier is coupled to the load capacitor and the inverting input terminal. Therefore, the operational amplifier in the sample mode operates with a unity gain (voltage follower), so that the level of the input signal of the non-inverting input terminal is sampled in the load capacitor of the output terminal. In the hold mode, the load capacity is supplied to the non-inverting input terminal of the operational amplifier, and the output terminal of the operational amplifier is coupled to the output and the inverting input terminal. Therefore, since the operational amplifier operates at the unity gain (voltage follower) also in the hold mode, the sample level of the load capacitor of the non-inverting input terminal is held at the output. The transistors functioning as the non-inverting input terminal and the inverting input terminal of the operational amplifier in the sample mode and the hold mode, respectively, are switched between the right and left P-channel MOS transistors in the differential pair. Further, transistors functioning as an input transistor and an output transistor in the current mirror of two load N-channel MOS transistors in the operational amplifier are switched between the right and left N-channel MOS transistors in the sample mode and the hold mode. The transistors functioning as output elements of the operational amplifiers in the sample mode and the hold mode are switched between right and left two grounded-source amplification N-channel MOS transistors. By the switch between the right and left transistors, the influence of the offset voltage due to mismatch of transistors configuring the operational amplifier can be reduced.
The following patent document 2 describes that, to reduce the influence on an A/D conversion result of the offset voltage of an amplifier in a special cyclic A/D converter, a change-over switch for switching two feedback capacitors between a differential input and a differential output of the amplifier between cross-couple connection and straight connection is used.
On the other hand, the following non-patent document 5 describes a gm control circuit for making mutual conductance “gm” of a rail-to-rail input circuit constant. The rail-to-rail input circuit includes an N-channel differential MOS transistor and a P-channel differential MOS transistor which are coupled in parallel against a change in common-mode input voltage. The gm control circuit includes a current switch P-channel MOS, a current switch N-channel MOS, a current mirror N-channel MOS, and a current mirror P-channel MOS.
A pair of P-channel MOS transistors generate a high-level common-mode voltage from a differential input signal. The high-level common-mode voltage is supplied to the source of the current switch P-channel MOS having a gate to which DC bias voltage is supplied. By the current mirror N-channel MOS coupled to the drain of the current switch P-channel MOS, the bias current of the source of the N-channel differential MOS transistor is controlled in proportional to the drain current of the current switch P-channel MOS. The pair of N-channel MOS transistors generate low-level common-mode voltage from the differential input signal, and the low-level common-mode voltage is supplied to the source of the current switch N-channel MOS having a gate to which the DC bias voltage is supplied. By the current mirror P-channel MOS coupled to the drain of the current switch N-channel MOS, the bias current of the source of the P-channel differential MOS transistor is controlled in proportional to the drain current of the current switch N-channel MOS.    [Non-patent document 1] Richard C. Jaeger, “Tutorial; Analog Data Acquisition Technology Part III—Sample-and-holds, Instrumentation Amplifiers, and Analog Multiplexers”, IEEE MICRO, November 1982, pp. 20 to 35    [Non-patent document 2] Christian C. Enz et al, “Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Sabilization”, PROCEEDINGS OF THE IEEE, VOL. 84, NO. 11, NOVEMBER 1996, PP. 1584 to 1614    [Non-patent document 3] Kenji Taniguchi, Semiconductor Series “CMOS analog circuit handbook for LSI designers”, CQ Publisher, Aug. 1, 2006, The fourth Edition, pp. 127 to 132    [Non-patent document 4] L. H. C. Ferreira et al, “CMOS implementation of precise sample-and-hold circuit with self-correction of the offset voltage”, IEE Proc.—Circuits Devices Syst, VOL. 152, NO. 5, OCTOBER 2005, PP. 451 to 455    [Non-patent document 5] Vladimir I. Prodanov et al, “New CMOS Universal Constant-Gm Input Stage”, 1998 IEEE International Conference on Electronics, Circuits and Systems, Vol. 2 7-10 Sep. 1998 pp. 359 to 362    [Patent document 1] Japanese Unexamined Patent Publication No. 2005-026805    [Patent document 2] Japanese Unexamined Patent Publication No. 2007-104531